Lanqi Technology has announced that it has completed development and system validation of an active electrical cable (AEC) solution compatible with PCIe 6.x and CXL 3.x standards. The company says the work places it among the first in China to claim system‑level validation for AECs at these next‑generation interface speeds, a domain traditionally dominated by international silicon and cable vendors.
Active electrical cables combine silicon-based signal conditioning and retiming with a cable harness so that very high data rates can be carried over short copper links with acceptable power, latency and signal integrity. PCIe 6.0 and CXL 3.0 raise the technical bar by doubling per‑lane raw signalling rates over PCIe 5.0 and adopting PAM4 modulation, while CXL 3.x expands coherence, memory pooling and switching features that data‑centre operators want for disaggregated architectures.
For cloud, telecom and AI datacentres the practical challenge is not only raw link speed but maintaining error‑free links across the physical medium. AEC implementations have to solve PAM4 noise margins, adaptive equalization, retiming, power delivery and thermal constraints inside a cable head, and they must interoperate with host PHYs, retimers and switches from multiple vendors. A domestic AEC that validates against PCIe/CXL test suites could therefore shorten integration cycles for Chinese system builders and reduce reliance on imported cable and chip solutions.
The announcement is as much about supply‑chain positioning as it is about technology. Western incumbents — including large connector and interconnect specialists and semiconductor companies that supply retimers and PHYs — have been the primary sources of validated high‑speed AECs. By developing an in‑house solution, Lanqi is signalling that Chinese vendors are moving from IP and chiplets toward complete end‑to‑end interconnect products that are central to server and accelerator platforms.
Caveats remain. The company’s statement describes R&D and system validation but does not specify production readiness, volume yields, interoperability certification with third‑party ecosystem partners, or which datacentre customers (if any) have been trialling the cables. Standards compliance alone does not guarantee field reliability or acceptance by hyperscalers, who typically require extensive multi‑vendor interoperability testing and long qualification cycles.
Still, the move fits a wider trend: Chinese silicon and systems companies are accelerating efforts to domestically source high‑speed I/O and memory interconnects as demand from AI training and inference clusters grows. If Lanqi can convert lab validation into stable mass production and pass multivendor interoperability audits, its AEC could be a meaningful step toward lowering barriers to deploying PCIe 6.0/CXL‑based fabrics inside Chinese datacentres and server OEMs.