For over half a century, the semiconductor industry has danced to the rhythmic beat of Moore’s Law, a spatial sprint to cram more transistors into smaller areas. But as the physical limits of silicon approach and geopolitical restrictions choke access to advanced lithography, Huawei is attempting to change the rules of the game entirely. At the 2026 International Symposium on Circuits and Systems, He Tingbo, President of HiSilicon, unveiled the 'τ (Tao) Law,' a strategic pivot that shifts the industry’s focus from spatial miniaturization to temporal optimization.
While traditional progress is measured in nanometers, the Tao Law measures progress by the reduction of the system's characteristic time constant, denoted as τ. This metric spans twelve orders of magnitude, from picosecond transistor switching to second-level data center workloads. Huawei argues that the true bottleneck in modern computing, particularly for AI, is no longer how fast a transistor can flip, but how long data must wait to move between memory and logic units. By optimizing the 'time ledger' of the entire stack, Huawei aims to deliver performance gains that transcend the limitations of physical process nodes.
Central to this shift is a breakthrough technique dubbed 'Logic Folding.' Unlike traditional 3D stacking which merely places memory on top of logic, Logic Folding involves a topological reconstruction of the logic circuit itself, distributing it across multiple vertically stacked active layers. This 'vertical city' approach significantly shortens the critical path of data, reducing interconnect latency and power consumption. Huawei's roadmap suggests that through these architectural innovations, their Kirin 2026 processors can achieve clock speeds of 3.1 GHz on mature nodes, with a trajectory toward 4 GHz by 2029.
This strategy is born of necessity as much as innovation. Having encountered the 'physical wall' of scaling earlier than its peers due to international sanctions, Huawei has spent six years redesigning its entire product portfolio, from Kirin mobile chips to Ascend AI processors, under this temporal framework. The goal is to achieve performance parity with global leaders not by chasing the 1.4nm horizon with inaccessible EUV machines, but by perfecting system-level integration and 're-fusing' the long-separated industries of logic and memory.