As the semiconductor industry hits the physical and economic walls of Moore’s Law, Huawei is attempting to rewrite the rulebook for silicon performance. He Tingbo, President of Huawei’s semiconductor arm, HiSilicon, has unveiled the second iteration of her “Tau Law” (τ), a theoretical framework that shifts the industry’s focus from the traditional shrinking of transistors to the optimization of time constants across chip architectures. This pivot is not merely a scientific exploration but a strategic necessity for a firm currently restricted from the world’s most advanced lithography tools.
The "V2" paper, published on ChinaXiv, moves from abstract theory to a concrete engineering blueprint for the post-Moore era. Central to this roadmap is the concept of "Logic Folding," an advanced 3D architectural approach designed to bypass the limitations of two-dimensional chip design. By optimizing the "Gear Ratio"—the proportion between hybrid bonding pitch and top-layer metal wiring—Huawei aims to achieve "cell-level continuous optimization." This effectively allows for performance gains that traditionally required more advanced, and currently inaccessible, manufacturing nodes.
Huawei’s internal roadmaps for its Kirin and Ascend processors, detailed in the update, reveal the scale of their ambition. The company expects its Kirin mobile CPUs to break the 4GHz clock speed barrier by 2029 through Logic Folding, while the Ascend AI series is projected to see a hundredfold increase in system-level integration by 2035. The roadmap indicates that while current AI chips like the Ascend 910C rely on mature Chiplet and 2.5D packaging, the transition to full 3D Logic Folding will begin around 2030.
Beyond individual chip speeds, the Tau Law addresses the systemic "memory wall" and the growing energy crisis in AI computing. He Tingbo argues that in massive AI clusters, over 80% of energy is wasted on data movement rather than computation. By implementing unified buses and near-package optical interconnects (Hi-ONE), Huawei is betting that the future of computing power will be defined not by who can etch the smallest transistors, but by who can most effectively shorten the distance data must travel between the chip, the server, and the rack.