Huawei’s semiconductor arm, HiSilicon, has signaled a significant leap in its quest to bypass traditional Moore’s Law limitations. Teresa He, the influential head of Huawei’s chip design division, recently released a refined Version 2 of her "Tao’s Law" paper. Officially titled "Time-Scaling Theory for Multi-level Electronic Systems," the document offers a theoretical and engineering roadmap for chip performance in an era where physical transistor shrinkage is reaching its limits.
Unlike the initial version released in May, this iteration provides granular engineering details and empirical data focused on "Logic Folding." This process involves stacking gate circuits vertically and connecting them through ultra-fine pitch hybrid bonding. By moving from horizontal layouts to three-dimensional structures, Huawei aims to achieve density and performance gains that mimic more advanced process nodes without relying solely on the world's most advanced lithography equipment.
The strategic pivot toward 3D IC (three-dimensional integrated circuits) creates a massive opening for China’s domestic semiconductor supply chain. Specifically, Electronic Design Automation (EDA) tools and advanced packaging are identified as the primary beneficiaries. Companies like Empyrean Technology, which offers the country's only full-process 3DIC design verification platform, are positioned to become indispensable as Chinese designers move toward these complex vertical architectures.
This development is more than a mere academic exercise; it represents a tactical shift in China’s broader technological self-reliance campaign. Blocked from acquiring the extreme ultraviolet (EUV) lithography machines needed for leading-edge 2nm or 3nm chips, Huawei is doubling down on system-level innovation. By mastering Logic Folding, Huawei seeks to maintain its competitive edge in the high-end smartphone and AI server markets despite the mounting geopolitical constraints.