At the 2026 International Symposium on Circuits and Systems (ISCAS) in Shanghai, He Tingbo, President of Huawei’s semiconductor arm, announced a paradigm shift that could redefine the global chip race. Facing prolonged restrictions on Advanced Extreme Ultraviolet (EUV) lithography, Huawei has formally proposed ‘Tao’s Law’ (τ Law). This new framework abandons the industry’s traditional obsession with 'geometric scaling'—the physical shrinking of transistors—in favor of 'time scaling,' focusing on the radical reduction of signal propagation latency.
For decades, Moore’s Law dictated that chip performance doubled by packing more transistors into smaller spaces. However, with physical limits approaching and geopolitical barriers blocking access to sub-5nm manufacturing tools, Huawei argues that this model is no longer the primary driver of value. According to He Tingbo’s recently published research, the AI era demands speed over size. In massive AI clusters, over 80% of energy is consumed by data movement rather than computation, suggesting that reducing the ‘characteristic time constant’ (τ) of a system is more critical than its physical dimensions.
The centerpiece of this strategy is ‘Logic Folding,’ a technique that uses 3D topological reorganization to compress logic circuits. Unlike standard 3D stacking or ‘Chiplet’ architectures, which often resemble stacking blocks, Huawei’s approach involves an integrated design that folds two-dimensional logic into three-dimensional space. This effectively shortens the physical distance signals must travel, allowing a chip manufactured on a mature process node to achieve the performance and density of a much more advanced generation.
Commercial evidence of this strategy is expected to debut this autumn with the Kirin 2026 processor. Huawei claims the chip achieved a 41% improvement in energy efficiency and a transistor density of 238 million per square millimeter—a feat that effectively bridges three years of traditional process node evolution without relying on EUV machines. By 2031, Huawei anticipates that these techniques will allow their chips to match the transistor density of 1.4nm processes, with clock speeds potentially exceeding 4GHz by 2035.
Despite the optimism, significant hurdles remain. The current global ecosystem of Electronic Design Automation (EDA) tools is built for planar, geometric scaling, not for full-scale logic folding. He Tingbo acknowledged that achieving this roadmap requires a complete overhaul of industry standards, including new thermal management systems and wafer-bonding techniques. Success will depend not just on Huawei’s ingenuity, but on whether the broader Chinese supply chain can build a self-sustaining ecosystem around this alternative technical path.