For over half a century, the semiconductor industry has bowed to Moore’s Law, the relentless doubling of transistors that fueled the digital age. Yet, as the physical limits of silicon atoms and the astronomical costs of extreme ultraviolet (EUV) lithography loom, the industry’s traditional path is fracturing. At the IEEE ISCAS 2026 symposium, Huawei’s semiconductor chief He Tingbo introduced a radical alternative: the “Tao (τ) Law.”
Named after the Greek letter used in physics to represent time constants, the Tao Law signals a pivot from “geometric scaling” to “time scaling.” Rather than focusing solely on shrinking the physical footprint of a transistor, Huawei’s strategy emphasizes the reduction of signal propagation latency. This shift is designed to bypass the bottlenecks of advanced manufacturing processes that have become the focal point of global trade tensions.
At the heart of this transition is a technique called “Logic Folding.” While traditional chip designs rely on two-dimensional layouts where signals often travel convoluted paths, logic folding rearranges these modules into multi-layered structures. By physically bringing distant logical units closer together, the system slashes resistance, capacitance, and the resulting energy waste, effectively boosting performance without requiring smaller transistors.
This architectural ingenuity is already moving from theory to the assembly line. Huawei claims to have utilized these principles in the production of 381 different chip models over the past six years. The upcoming “Kirin 2026” processor is slated to be the first consumer-facing implementation of logic folding, aiming to achieve transistor density equivalent to a 1.4nm process by 2031 while utilizing more accessible manufacturing nodes.
For China, the Tao Law represents a declaration of independence from Western-controlled lithography supply chains. By optimizing across the full stack—from devices and circuits to software and system architecture—Huawei is betting that integrated system innovation can compensate for the lack of the world's most advanced chip-making machinery. It is a pragmatic shift from chasing the smallest nanometer to maximizing the efficiency of the available silicon.