Broadcom has begun shipping what it calls the industry’s first custom compute SoC built on its 3.5D eXtreme Dimension System in Package (XDSiP) platform, and its marketing executives are bold about the market opportunity. The company says the modular platform — which blends 2.5D interposers with face‑to‑face 3D‑IC integration — allows two separate silicon dies to be fused into a single package, boosting inter-die bandwidth and cutting power for AI workloads. Broadcom’s product marketing vice‑president Harish Bharadwaj told media the firm believes it can sell at least one million of these stacked chips by 2027, a milestone Broadcom frames as evidence that heterogeneous stacking has reached commercial scale.
The first customer to test the approach is Fujitsu, which is building a data‑centre chip that pairs a TSMC‑fabricated 2nm compute die with a 5nm companion die in Broadcom’s stacking process. Broadcom describes the XDSiP architecture as the foundation for the next generation of XPUs — specialised accelerators aimed at AI inference and training — and says it spent roughly five years validating and iterating the design before bringing it to market. Engineers are already exploring more aggressive topologies, with an ultimate design target of up to eight layers and two dies per layer.
Broadcom’s commercial model is a collaborative one: it typically converts customer concepts into manufacturable physical layouts and relies on foundries such as TSMC to produce the wafers that are then fused into stacked packages. That customer‑centric approach has attracted large cloud and enterprise partners; Broadcom says bespoke engagements with firms including Google have helped drive its chip business, and it expects AI‑related chip revenue to roughly double year‑on‑year in the current fiscal first quarter to about $8.2bn.
Technically, Broadcom’s announcement underscores a wider industry pivot from pure transistor scaling to advanced packaging and heterogeneous integration. As node scaling becomes more expensive and returns diminish, chipmakers are increasingly stitching together best‑of‑breed dies — mixing process nodes and functions — to achieve performance and power targets. Face‑to‑face bonding and 2.5D interposers can dramatically reduce latencies and energy per bit moved compared with traditional multi‑chip modules, making them attractive for memory‑heavy AI workloads.
Commercially, the one‑million‑unit target is ambitious but plausible. Hyperscalers and large enterprise customers buy chips in volumes where a million units is meaningful but not outlandish, especially if Broadcom’s packaging lets customers avoid the cost and risk of monolithic node migration. Broadcom plans more XDSiP‑based products later this year and three additional samples by 2027, signalling a roadmap designed to convert early engineering wins into broader adoption.
Strategically, the move reinforces TSMC’s centrality to advanced compute: Broadcom’s stacking still depends on leading‑edge wafer production, even as it reduces the pressure to cram an entire design onto a single newest‑node die. For competitors and national chip initiatives, it also raises the bar on packaging capabilities and integration ecosystems. If Broadcom’s platform delivers the promised power and bandwidth gains at scale, it will accelerate a shift toward chiplet and stacked architectures across data centres and could reshape how supply chains and design partnerships are organised.
For buyers and regulators the implications are twofold. Customers gain a more flexible route to high performance without sole reliance on a single node, but the rise of fused multi‑die packages complicates provenance and export controls, since functionality can be split across dies made in different jurisdictions. Broadcom’s commercial success with XDSiP will therefore matter not only for performance and cost curves but for how industry and policy cope with increasingly modular semiconductor products.